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q-smint ? o 2b1 q s econd gen. m odular i sdn nt (o rdinary) pef 80912/80913 version 1.3 data sheet, ds 1, march 2001 wired communications never stop thinking.
edition march 2001 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications q-smint ? o 2b1 q s econd gen. m odular i sdn nt (o rdinary) pef 80912/80913 version 1.3 data sheet, ds 1, march 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 80912/80913 revision history: march 2001 ds 1 previous version: preliminary data sheet 10.00 page subjects (major changes since last revision) all editorial changes, addition of notes for clarification etc. table 1 , chapter 1.3 introduced new version 80913 with extended performance of the u-interface chapter 2.4.5.1 s-transceiver nt state machine: added note : ?by setting the test mode pins tm0-2 to ?010? / ?011?: continuous pulses / single pulses, the s-transceiver starts sending the corresponding test signal, but no state transition is invoked.? chapter 2.4.5.1 c/i commands: removed ?unconditional command? from description c/i-command ?dr? figure 16 corrected figure: ?complete activation initiated by exchange?: info4 is sent by the nt (not byte) chapter 4.1 absolute maximum ratings: maximum voltage on vdd: 4.2v (before: 4.6v) chapter 4.1 refined references for esd requirements:? ...(cdm), eia/jesd22-a114b (hbm) ---? chapter 4.2 input/output leakage current set to 10a (before: 1a) table 19 u-transceiver characteristics: enhanced s/n+d for 80913 and threshold level for 80912 and 80913 distinguished chapter 4.6.3 parameters of the uvd/por circuit: defined reduced range of hysteresis: min. 30mv/max. 90mv relaxed upper limit of detection threshold to 2.92v (before: 2.9v) defined max. rising vdd for power-on chapter 6.3 external circuitry for t-smint updated
pef 80912/80913 table of contents page data sheet 2001-03-29 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 features pef 80912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 features pef 80913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 not supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.7 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.7.1 specific pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.8 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 iom?-2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 2b1q frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 cyclic redundancy check / febe bit . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 scrambling/ descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.4 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.5 state machine for line activation / deactivation . . . . . . . . . . . . . . . . . . 20 2.3.5.1 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.5.2 standard nt state machine (iec-q / ntc-q compatible) . . . . . . . . 21 2.3.5.3 inputs to the u-transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.5.4 outputs of the u-transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.5.5 description of the nt-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.6 metallic loop termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.1 line coding, frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.2 s/q channels, multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.3 data transfer between iom?-2 and s0 . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.4 loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.5.1 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 layer 1 activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.1 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . . 41 3.1.2 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.3 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4 partial activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.5 activation from exchange with u active . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.6 activation from te with u active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
pef 80912/80913 table of contents page data sheet 2001-03-29 3.1.7 partial deactivation with u active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.8 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 layer 1 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.1 loopback no.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.1.1 complete loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.1.2 loopback no.2 - single channel loopbacks . . . . . . . . . . . . . . . . . . . 50 3.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.3 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3.4 oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.5 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6.1 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.6.3 undervoltage detection characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6 appendix: differences between q- and t-smint?o . . . . . . . . . . . . . . . 69 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.1 u-interface conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.2 u-transceiver state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2.3 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
pef 80912/80913 list of figures page data sheet 2001-03-29 figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3 application example q-smint?o: standard nt1 . . . . . . . . . . . . . . . . 12 figure 4 iom ? -2 frame structure of the q-smint?o . . . . . . . . . . . . . . . . . . . . 14 figure 5 u-superframe structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 u-basic frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 u2b1q framer - data flow scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 u2b1q deframer - data flow scheme . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 explanation of state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 standard nt state machine (iec-q / ntc-q compatible) (footnotes: see ?dependence of outputs? on page 26 ) 21 figure 11 pulse streams selecting quiet mode . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13 frame structure at reference points s and t (itu i.430). . . . . . . . . . 33 figure 14 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . 41 figure 17 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18 complete deactivation initiated by exchange . . . . . . . . . . . . . . . . . . . 43 figure 19 partial activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 20 activation from lt with u active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21 activation from te with u active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 22 partial deactivation with u active . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 25 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 26 external circuitry u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27 external circuitry s-interface transmitter . . . . . . . . . . . . . . . . . . . . . . 54 figure 28 external circuitry s-interface receiver . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 30 maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . . 61 figure 31 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 32 iom?-2 interface - bit synchronization timing . . . . . . . . . . . . . . . . . . 63 figure 33 iom-2 interface - frame synchronization timing . . . . . . . . . . . . . . . . 63 figure 34 reset input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 35 undervoltage control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 36 ntc-q compatible state machine q-smint?o: 2b1q . . . . . . . . . . . . 71 figure 37 iec-t/ntc-t compatible state machine t-smint?o: 4b3t . . . . . . . . 72 figure 38 external circuitry q- and t-smint?o . . . . . . . . . . . . . . . . . . . . . . . . . 74
pef 80912/80913 list of tables page data sheet 2001-03-29 table 1 nt products of the 2nd generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4 lp2i states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6 u-superframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7 u - transceiver c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8 timers used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9 u-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10 states with operational data on iom?-2 . . . . . . . . . . . . . . . . . . . . . . . 26 table 11 signal output on uk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12 c/i-code output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13 ansi maintenance controller states . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14 u-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 15 s-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 16 crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17 maximum input currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18 s-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 19 u-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 20 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 21 reset input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 22 parameters of the uvd/por circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 23 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 24 related documents to the u-interface. . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 26 dimensions of external components. . . . . . . . . . . . . . . . . . . . . . . . . . 75
pef 80912/80913 overview data sheet 1 2001-03-29 1 overview the pef 80912 / 80913 (q-smint ? o) offers all nt1 features known from the peb / pef 8091 [11] and can hence replace the latter in all nt1 applications. table 1 summarizes the 2nd generation nt products. table 1 nt products of the 2nd generation pef80912 pef80913 pef81912 pef81913 pef82912 pef82913 q-smint ? o q-smint ? ix q-smint ? i package p-mqfp-44 p-mqfp-64 p-tqfp-64 p-mqfp-64 p-tqfp-64 register access no u+s+hdlc+ iom ? -2 u+s+ iom ? -2 access via n.a. parallel (or sci or iom ? -2) parallel (or sci or iom ? -2) mclk, watchdog timer, sds, bcl, d- channel arbitration, iom ? -2 access and manipulation etc. provided no yes yes hdlc controller no yes no nt1 mode available yes (only) no no extended u- performance 20kft no yes no yes no yes
pef 80912/80913 overview data sheet 2 2001-03-29 1.1 references [1] ts 102 080, transmission and multiplexing ; isdn basic rate access; digital transmission system on metallic local lines, etsi, november 1998 [2] t1.601-1998 (revision of ansi t1.601-1992), isdn-basic access interface for use on metallic loops for application on the network side of the nt (layer 1 specification), ansi, 1998 [3] st/laa/elr/dnp/822, cnet, france [4] rc7355e, 2b1q generic physical layer specification, british telecommunications plc., 1997 [5] fza ts 0095/01:1997-10, technische spezifikationen f r netzabschlu ? ger ? te f r den isdn basisanschlu ? (nt-ba), post & telekom austria, 1997 [6] pr ets 300 012 draft, isdn; basic user network interface (uni), etsi, november 1996 [7] t1.605-1991, isdn-basic access interface for s and t reference points (layer 1 specification), ansi, 1991 [8] i.430, isdn user-network interfaces: layer 1 recommendations, itu, november 1988 [9] iec-q, isdn echocancellation circuit, peb 2091 v4.3, user ? s manual 02.95, siemens ag, 1995 [10] sbcx, s/t bus interface circuit extended, peb 2081 v3.4, user ? s manual 11.96, siemens ag, 1996 [11] ntc-q, network termination controller (2b1q), peb / pef 8091 v1.1, data sheet 10.97, siemens ag, 1997 [12] intc-q, intelligent network termination controller (2b1q), peb / pef 8191 v1.1, data sheet 10.97, siemens ag, 1997 [13] iom ? -2 interface reference guide, siemens ag, 03.91 [14] scout-s(x), siemens codec with s/t-transceiver, psb 2138x v1.3, preliminary data sheet 8.99, infineon technologies, 1999 [15] pita, pci interface for telephony/data applications v0.3, sican gmbh, september 1997 [16] dual channel slicofi-2, hv-slic; duslic; peb3265, 4265, 4266; data sheet ds2, infineon technologies, july 2000.
pef 80912/80913 overview data sheet 3 2001-03-29 2b1q second gen. modular isdn nt (ordinary) q-smint ? o pef 80912/80913 version 1.3 1.2 features pef 80912 features known from the peb / pef 8091 single chip solution including u- and s-transceiver perfectly suited for the nt1 in the isdn fully automatic activation and deactivation u-interface (2b1q) conform to etsi [1], ansi [2] and cnet [3]: ? meets all transmission requirements on all etsi, ansi and cnet loops with margin ? conform to british telecom ? s rc7355e [4] ? compliant with etsi 10 ms micro interruptions ? mlt input and decode logic (ansi [2]) s/t-interface conform to etsi [6], ansi [7] and itu [8] ? supports point-to-point and bus configurations ? meets and exceeds all transmission requirements pin programmable cso-bit optional iom ? -2 interface eases chip testing and evaluation activation status led supported p-mqfp-44-2 p-mqft-44 type package pef 80912/80913 p-mqft-44
pef 80912/80913 overview data sheet 4 2001-03-29 new features reduced number of external components for external u-hybrid required optional use of up to 2x20 ? resistors on the line side of the transformer (e.g. ptcs) pin uref and the according external capacitor removed improved esd (2 kv instead of <850 v) inputs accept 3.3 v and 5 v i/o (open drain) accepts pull-up to 3.3 v 1) pin compatible with t-smint ? o (2nd generation) led indicates loopback 2 (lbbd) power-on reset and undervoltage detection with no external components lowest power consumption due to ? low power cmos technology (0.35) ? newly optimized low power libraries ? high output swing on u- and s-line interface leads to minimized power consumption ? single 3.3 volt power supply 200 mw (ntc-q: 285 mw) power consumption with random data over etsi loop 2. 15 mw typical power consumption in power down (ntc-q: 28 mw) 1.3 features pef 80913 the q-smint ? o pef 80913 provides all features of the pef 80912. additionally, a significantly enhanced performance of the u-interface as compared to etsi [1], ansi [2] and cnet [3] requirements is guaranteed: transparent transmission on 20kft awg26 with a ber < 10 -7 (without noise). 1) pull-ups to 5 v must be avoided. a so-called ? hot-electron-effect ? would lead to long term degradation.
pef 80912/80913 overview data sheet 5 2001-03-29 1.4 not supported are ... integrated u-hybrid ? nt-star ? with star point on the iom ? -2 bus (already not supported in ntc-q). the oscillator architecture was changed with respect to the ntc-q to reduce power consumption. as a consequence, the q-smint ? o always needs a crystal and pin xin can not be connected to an external clock as it was possible for iec-q and ntc-q. this does not limit the use of the q-smint ? o in nts since all nt designs use crystals anyway. 1.5 pin configuration figure 1 pin configuration /vdddet /rsto vdda_sr vssa_sr ps1 xout xin bout vdda_ux vssa_ux aout fsc dcl bus cso aua vssd vddd tm2 tm1 /act 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 q-sminto pef 80912 pef 80913 vssa_ur bin /rst dio /tll vdda_ur dd du /lp2i ps2 sx1 tp1 vssa_sx vdda_sx sr1 sr2 sx2 ain t p 2 tm0 mti vssd vddd pin_2.vsd
pef 80912/80913 overview data sheet 6 2001-03-29 1.6 block diagram figure 2 block diagram clock generation s-transceiver u-tansceiver por/uvd test modes iom-2 interface u/s transceiver control factory test xin xout aout bout ain bin tm1 tm0 sx2 sx1 sr2 sr1 led ps1 ps2 mti tp1 act tll cso aua bus dd du dcl fsc tm2 dio block diagram.vsd rst rsto vdddet tp2 lp2i
pef 80912/80913 overview data sheet 7 2001-03-29 1.7 pin definitions and functions table 2 pin definitions and functions pin symbol type function 2 vdda_ur ? supply voltage for u-receiver (3.3 v 5%) 1 vssa_ur ? analog ground (0 v) u-receiver 42 vdda_ux ? supply voltage for u-transmitter (3.3 v 5%) 43 vssa_ux ? analog ground (0 v) u-transmitter 36 vdda_sr ? supply voltage for s-receiver (3.3 v 5%) 37 vssa_sr ? analog ground (0 v) s-receiver 31 vdda_sx ? supply voltage for s-transmitter (3.3 v 5%) 30 vssa_sx ? analog ground (0 v) s-transmitter 19 vddd ? supply voltage digital circuits (3.3 v 5%) 20 vssd ? ground (0 v) digital circuits 8 vddd ? supply voltage digital circuits (3.3 v 5%) 9 vssd ? ground (0 v) digital circuits 22 fsc o frame sync: 8-khz frame synchronization signal 21 dcl o data clock: iom ? -2 interface clock signal (double clock): 512 khz 25 lp2i o loopback 2 indication: can directly drive a led (4 ma). 0: lbbd received, loopback 2 closed 1: loopback 2 not closed. 23 dd o data downstream: data on the iom ? -2 interface 24 du o data upstream: data on the iom ? -2 interface
pef 80912/80913 overview data sheet 8 2001-03-29 7dioi disable iom ? -2: 1: fsc, dcl, du and dd high z 0: fsc, dcl, du and dd push-pull 16 aua i auto u activation: 1: u-transceiver attempts one automatic activation after reset. tie to ? 0 ? in applications that do not require auto-start after reset. 17 cso i cold start only: ? 1 ? selects cso-bit to ? 0 ? . (normal) ? 0 ? selects cso-bit to ? 1 ? . (special cases) the pin only controls the cso-bit in the u- frame. the u-transceiver itself is always a warm-start transceiver according to ansi and etsi. 18 bus i (pu) bus mode on s-interface: 1: passive s-bus (fixed timing) 0: point-to-point / extended passive s-bus (adaptive timing) 5rst i reset: low active reset input. schmitt-trigger input with hysteresis of typical 360 mv. tie to ? 1 ? if not used. 6rsto od reset output: low active reset output. 10 tll i triple-last-look select validation algorithm for received m4 bit towards state machine: ? 0 ? : crc & tll ? 1 ? : crc 13 tm0 i test mode 0 selects test pattern (see page 11 ). 14 tm1 i test mode 1 selects test pattern (see page 11 ). 15 tm2 i test mode 2 selects test pattern (see page 11 ). table 2 pin definitions and functions (cont ? d) pin symbol type function
pef 80912/80913 overview data sheet 9 2001-03-29 28 sx1 o s-bus transmitter output ( positive ) 29 sx2 o s-bus transmitter output ( negative ) 32 sr1 i s-bus receiver input 33 sr2 i s-bus receiver input 40 xin i crystal 1: connected to a 15.36 mhz crystal 39 xout o crystal 2: connected to a 15.36 mhz crystal 44 aout o differential u-interface output 41 bout o differential u-interface output 3aini differential u-interface input 4bini differential u-interface input 34 vdddet i vdd detection: this pin selects if the v dd detection is active ( ? 0 ? ) and reset pulses are generated on pin rsto or whether it is deactivated ( ? 1 ? ) and an external reset has to be applied on pin rst. 11 mti i metallic termination input. input to evaluate metallic termination pulses. tie to ? 1 ? if not used. 38 ps1 i power status (primary). the pin status is passed to the overhead bit ? ps1 ? in the u frame to indicate the status of the primary power supply ( ? 1 ? = ok). 26 ps2 i power status (secondary). the pin status is passed to the overhead bit ? ps2 ? in the u frame to indicate the status of the secondary power supply ( ? 1 ? = ok). table 2 pin definitions and functions (cont ? d) pin symbol type function
pef 80912/80913 overview data sheet 10 2001-03-29 pu: internal pull-up resistor (typ. 100 a) i: input o: output (push-pull) od: output (open drain) 1.7.1 specific pins led pins act , lp2i a led can be connected to pin act to display four different states (off, slow flashing, fast flashing, on). it displays the activation status of the u- and s-transceiver according to table 3 . with: u_deactivated : ? deactivated state ? as defined in chapter 2.3.5.5 . u_activated : ? synchronized 1 ? , ? synchronized 2 ? , ? wait for act ? , ? transparent ? , ? error s/ t ? , ? pend. deact. s/t ? , ? pend. deact. u ? as defined in chapter 2.3.5.5 . s-activated : ? activated state ? as defined in chapter 2.4.5 . 12 act o activation led. indicates the activation status of u- and s- transceiver. can directly drive a led (4 ma). 27 tp1 i test pin 1. used for factory device test. tie to v ss 35 tp2 i test pin 2. used for factory device test. tie to v ss table 3 act states pin act led u_deactivated u_activated s_activated v dd off 1 x x 8hz 8hz 0 0 x 1hz 1hz 0 1 0 gnd on 0 1 1 table 2 pin definitions and functions (cont ? d) pin symbol type function
pef 80912/80913 overview data sheet 11 2001-03-29 note: optionally, pin act can drive a second led with inverse polarity (connect this additional led to 3.3 v only). another led can be connected to pin lp2i to indicate an active loopback 2 according to table 4 . test modes different test patterns on the u- and s-interface can be generated via pins tm0-2 according to table 5 . table 4 lp2i states pin lp2i led eoc-command lbbd v dd off received no eoc-lbbd or received rtn after an lbbd command. gnd on eoc-command lbbd (50) has been received. complete analog loop is being closed on the s-interface. table 5 test modes tm0 tm1 tm2 u-transceiver s-transceiver 0 0 0 reserved for future use. normal operation in this version. 001 0 1 0 normal operation 96 khz 1) continuous pulses 1) the s-transceiver transmits pulses with alternating polarity at a rate of 192 khz resulting in a 96 khz envelope. 0 1 1 2 khz 2) single pulses 2) the s-transceiver transmits pulses with alternating polarity at a rate of 4 khz resulting in a 2 khz envelope. 1 0 0 data through 3) 3) forces the u-transceiver into the state ? transparent ? where it transmits signal sn3t. normal operation 1 0 1 send single pulses 4) 4) forces the u-transceiver to go into state ? test ? and to send single pulses. the pulses are issued at 1.5 ms intervals and have a duration of 12.5 s. 1 1 0 quiet mode 5) 5) the u-transceiver is hardware reset. 1 1 1 normal operation
pef 80912/80913 overview data sheet 12 2001-03-29 1.8 system integration the q-smint ? o provides nt1 functionality without a microcontroller being necessary. special selections can be done via pin strapping (cso, tll , bus, etc.). the device has no p interface. the iom ? -2 interface serves only for monitoring and debugging purposes. it can be regarded as a window to the internal iom ? -2. . figure 3 application example q-smint ? o: standard nt1 s u idcc peb2023 mlt pin strap - mode selection iom-2 leds q-sminto pef80912 pef 80913 - disable iom - 2 - p-to-p/busselection - m4 bit validation algorithm - cso - bit polarity - u - activation after reset - test pattern selection - loop 2 ind. -activation status u - interface s/t - interface nt1_appl.vsd dc/dc-converter
pef 80912/80913 functional description data sheet 13 2001-03-29 2 functional description 2.1 reset generation external reset input at the rst input an external reset can be applied forcing the q-smint ? o in the reset state. this external reset signal is additionally fed to the rsto output. reset ouput if vdddet is active, then the deactivation of a reset output on rsto is delayed by t deact (see table 22 ). reset generation the q-smint ? o has an on-chip reset generator based on a power-on reset (por) and under voltage detection (uvd) circuit (see table 22 ). the por/uvd requires no external components. the por/uvd circuit can be disabled via pin vdddet . the requirements on v dd ramp-up during power-on reset are described in chapter 4.6.3 . clocks and data lines during reset during reset the data clock (dcl) and the frame synchronization (fsc) keep running. during reset dd and du are high; with the exception of: the output c/i code from the u-transceiver on dd is ? dr ? = 0000 the output c/i code from the s-transceiver on du is ? tim ? = 0000.
pef 80912/80913 functional description data sheet 14 2001-03-29 2.2 iom ? -2 interface the iom ? -2 interface always operates in nt mode according to the iom ? -2 reference guide [13]. 2.2.1 iom ? -2 functional description the iom ? -2 interface consists of four lines: fsc, dcl, dd, du. the rising edge of fsc indicates the start of an iom ? -2 frame. the dcl clock signal synchronizes the data transfer on both data lines du and dd. the dcl is twice the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle. note: it is not possible to write any data via iom ? -2 into the q-smint ? o. the iom ? -2 interface can be enabled/disabled with pin dio. the fsc signal is an 8 khz frame sync signal. the number of pcm timeslots on the transmit line is determined by the frequency of the dcl clock, with the 512 khz clock 1 channel consisting of 4 timeslots is available. iom ? -2 frame structure of the q-smint ? o the frame structure on the iom ? -2 data ports (du,dd) of the q-smint ? o with a dcl clock of 512 khz is shown in figure 4 . figure 4 iom ? -2 frame structure of the q-smint ? o the frame is composed of one channel: channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (not available in q-smint ? o) and a command/indication channel (ci0) for control of e.g. the u-transceiver.
pef 80912/80913 functional description data sheet 15 2001-03-29 2.3 u-transceiver the state machine of the u-transceiver is based on the nt state machine in the peb / pef 8091 documentation [11]. basic configurations are selected via pin strapping. 2.3.1 2b1q frame structure transmission on the u 2b1q -interface is performed at a rate of 80 kbaud. the code used is reducing two bits to one quaternary symbol (2b1q). data is grouped together into u-superframes of 12 ms each. each superframe consists of eight basic frames which begin with a synchronization word and contain 222 bits of information. the first basic frame of a superframe starts with an inverted synchword (isw) compared to the other basic frames (sw). the structure of one u-superframe is illustrated in figure 5 and figure 6 . figure 5 u-superframe structure figure 6 u-basic frame structure out of the 222 information bits 216 contain 2b + d data from 12 iom ? -frames, the remaining 6 bits are used to transmit maintenance information. thus 48 maintenance bits are available per u-superframe. they are used to transmit two eoc-messages (24 bit), 12 maintenance (overhead) bits and one checksum (12 bit). isw 1. basic frame sw 2. basic frame . . . sw 8. basic frame <---12 ms---> (i) sw (inverted) synch word 18 bit (9 quat) 12 2b + d user data 216 bits (108 quat) m1 ? m6 maintenance data 6 bits (3 quat) <---1,5 ms--->
pef 80912/80913 functional description data sheet 16 2001-03-29 ? isw inverted synchronization word (quad): ? 3 ? 3 + 3 + 3 + 3 ? 3 + 3 ? 3 ? 3 ? sw synchronization word (quad): + 3 + 3 ? 3 ? 3 ? 3 + 3 ? 3 + 3 + 3 ? crc cyclic redundancy check ? eoc embedded operation channel a = address bit d/m = data / message bit i = information (data / message) ? act activation bit act = (1) ? > layer 2 ready for communication table 6 u-superframe format fram- ing 2b + d overhead bits (m1 ? m6) quat position s 1 ? 9 10 ? 117 118 s 118 m 119 s 119 m 120 s 120 m bit position s 1 ? 18 19 ? 234 235 236 237 238 239 240 super frame # basic frame # sync word 2b + d m1 m2 m3 m4 m5 m6 11 isw2b + d eoc a1 eoc a2 eoc a3 act/ act 11 2sw2b + d eoc dm eoc i1 eoc i2 dea / ps1 1 febe 3sw2b + d eoc i3 eoc i4 eoc i5 sco/ ps2 crc1 crc2 4sw2b + d eoc i6 eoc i7 eoc i8 1/ ntm crc3 crc4 5sw2b + d eoc a1 eoc a2 eoc a3 1/ cso crc5 crc6 6sw2b + d eoc dm eoc i1 eoc i2 1 crc7 crc8 7sw2b + d eoc i3 eoc i4 eoc i5 uoa / sai crc9 crc 10 8sw2b + d eoc i6 eoc i7 eoc i8 aib / nib crc 11 crc 12 2,3 ? lt- to nt dir. > / < nt- to lt dir.
pef 80912/80913 functional description data sheet 17 2001-03-29 ? dea deactivation bit dea = (0) ? > lt informs nt that it will turn off ? cso cold start only cso = (1) ? > nt-activation with cold start only ? uoa u-only activation uoa = (0) ? > u-only activated ? sai s-activity indicator sai = (0) ? > s-interface is deactivated ? febe far-end block error febe = (0) ? > far-end block error occurred ? ps1 power status primary source ps1 = (1) ? > primary power supply ok ? ps2 power status secondary source ps2 = (1) ? > secondary power supply ok ? ntm nt-test mode ntm = (0) ? > nt busy in test mode ? aib alarm indication bit aib = (0) ? > interruption (according to ansi) ? nib network indication bit nib = (1) ? > no function (reserved for network use) ? sco start on command only bit ? 1 (currently not defined by ansi/etsi) can be accessed by the system interface for proprietary use the principle signal flow is depicted in figure 7 and figure 8 . the data is first grouped in bits that are covered by the crc and bits that are not. after the crc generation the bits are arranged in the proper sequence according to the 2b1q frame format, encoded and finally transmitted. in receive direction the data is first decoded, descrambled, deframed and handed over for further processing. figure 7 u 2b1q framer - data flow scheme scrambler sync/inv. sync tone/pulse patterns m u x 2b1q encoding m u x crc generation m1,2,3 (eoc) m5,6 except crc 2b+d m4 u 2b1q -fram er ( m- bit handling acc. t o etr080) control m u x m u x ufr amer .emf 2b+d, m4
pef 80912/80913 functional description data sheet 18 2001-03-29 figure 8 u 2b1q deframer - data flow scheme 2.3.2 cyclic redundancy check / febe bit an error monitoring function is implemented covering the 2b + d and m4 data transmission of a u-superframe by a cyclic redundancy check (crc). the computed polynomial is: g (u) = u 12 + u 11 + u 3 + u 2 + u + 1 (+ modulo 2 addition) the check digits (crc bits crc1, crc2, ? , crc12) generated are transmitted in the u-superframe. the receiver will compute the crc of the received 2b + d and m4 data and compare it with the received crc-bits generated by the transmitter. a crc-error will be indicated to both sides of the u-interface, as a nebe (near-end block error) on the side where the error is detected, as a febe (far-end block error) on the remote side. the febe-bit will be placed in the next available u-superframe transmitted to the originator. 2.3.3 scrambling/ descrambling the scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are transmitted. the scrambling / descrambling process is controlled fully by the q- smint ? o. hence, no influence can be taken by the user. d e m u x m1,2,3 (eoc) m5,6 except crc 2b+d m4 u 2b1q -deframer (m-bit handling acc. to etr080) control descrambler d e m u x crc check 2b1q decoding sync/inv. sync d e m u x udeframer.emf
pef 80912/80913 functional description data sheet 19 2001-03-29 2.3.4 c/i codes the operational status of the u-transceiver is controlled by the control/indicate channel (c/i-channel). table 7 presents all defined c/i codes. an indication is issued permanently by the u-transceiver on dd until a new indication needs to be forwarded. because a number of states issue identical indications it is not possible to identify every state individually. ai: activation indication ail: activation indication loop ar: activation request arl: activation request local loop dc: deactivation confirmation di: deactivation indication dr: deactivation request table 7 u - transceiver c/i codes code in out 0000 tim dr 0001 res ? 0010 ?? 0011 ?? 0100 ei1 ei1 0101 ssp ? 0110 dt ? 0111 ? pu 1000 ar ar 1001 ?? 1010 arl arl 1011 ?? 1100 ai ai 1101 ?? 1110 ? ail 1111 di dc
pef 80912/80913 functional description data sheet 20 2001-03-29 dt: data through test mode ei1: error indication 1 pu: power-up res: reset ssp: send single pulses test mode tim: timing request 2.3.5 state machine for line activation / deactivation 2.3.5.1 notation the state machines control the sequence of signals at the u-interface that are generated during the start-up procedure. the informations contained in the following state diagrams are: ? state name ? u-signal transmitted ? overhead bits transmitted ? c/i-code transmitted ? transition criteria ? timers figure 9 shows how to interpret the state diagrams. figure 9 explanation of state diagram notation combinations of transition criteria are possible. logical ? and ? is indicated by ? & ? (tn & dc), logical ? or ? is written ? or ? and for a negation ? / ? is used. the start of a timer is indicated with ? txs ? ( ? x ? being equivalent to the timer number). timers are always started when entering the new state. the action resulting after a timer has expired is indicated by the path labelled ? txe ? . state name signal transmitted to u-interface (general) single bit transmitted to u-interface indication transmitted on c/i-channel (dout) in out itd04257.vsd
pef 80912/80913 functional description data sheet 21 2001-03-29 2.3.5.2 standard nt state machine (iec-q / ntc-q compatible) figure 10 standard nt state machine (iec-q / ntc-q compatible) (footnotes: see ? dependence of outputs ? on page 26 ) sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e&di lsuor(/lof&t13e) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu
pef 80912/80913 functional description data sheet 22 2001-03-29 note: the test modes ?data through? (dt), ?send single pulses? (ssp) and ?quiet mode? (qm) can be generated via pins tm0-2 according to table 5 . if the metallic loop termination is used, then the u-transceiver is forced into the states ?reset? and ?transparent? by valid pulse streams on pin mti according to table 13 . 2.3.5.3 inputs to the u-transceiver: c/i-commands: ai activation indication the downstream device issues this indication to announce that its layer-1 is available. the u-transceiver informs the lt side by setting the ? act ? bit to ? 1 ? . ar activation request the u-transceiver is requested to start the activation process by sending the wake- up signal tn. arl activation request local loop-back the u-transceiver is requested to operate an analog loop-back (close to the u- interface) and to begin the start-up sequence by sending sn1 (without starting timer t1). this command may be issued only after the u-transceiver has been hw- or sw- reset. this eases that the ec- and eq-coefficient updating algorithms converge correctly. the arl-command has to be issued continuously as long as the loop-back is required. di deactivation indication this indication is used during a deactivation procedure to inform the u-transceiver that it may enter the deactivated (power-down) state. dt data through this unconditional command is used for test purposes only and forces the u- transceiver into the ? transparent ? state. ei1 error indication 1 the downstream device indicates an error condition (loss of frame alignment or loss of incoming signal). the u-transceiver informs the lt-side by setting the act-bit to ? 0 ? thus indicating that transparency has been lost. res reset unconditional command which resets the u-transceiver. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. tim timing the u-transceiver is requested to enter state ? iom ? -2 awaked ? .
pef 80912/80913 functional description data sheet 23 2001-03-29 u-interface events: act = 0/1 act-bit received from lt-side. ? act = 1 requests the u-transceiver to transmit transparently in both directions. in the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is synchronized. ? act = 0 indicates that layer-2 functionality is not available. dea = 0/1 dea-bit received from the lt-side ? dea = 0 informs the u-transceiver that a deactivation procedure has been started by the lt-side. ? dea = 1 reflects the case when dea = 0 was detected by faults due to e.g. transmission errors and allows the u-transceiver to recover from this situation. uoa = 0/1 uoa-bit received from network side ? uoa = 0 informs the u-transceiver that only the u-interface is to be activated. the s/t-interface must be deactivated. ? uoa = 1 requests the s/t-interface (if present) to activate. timers the start of timers is indicated by txs, the expiry by txe. table 8 shows which timers are used: table 8 timers used timer duration (ms) function state t1 15000 supervisor for start-up t7 40 hold time receive reset t11 9 tn-transmission alerting t12 5500 supervisor ec-converge ec-training t13 15000 frame synchronization pend. receive reset t14 0.5 hold time pend. timing t20 10 hold time wait for sf
pef 80912/80913 functional description data sheet 24 2001-03-29 2.3.5.4 outputs of the u-transceiver: the following signals and indications are issued on iom ? -2 (c/i-indications) and on the u-interface (predefined u-signals): c/i-indications ai activation indication the u-transceiver has established transparency of transmission. the downstream device is requested to establish layer-1 functionality. ail activation indication loopback the u-transceiver has established transparency of transmission. the downstream device is requested to establish a loopback #2. ar activation request the downstream device is requested to start the activation procedure. arl activation request loop-back the u-transceiver has detected a loop-back 2 command in the eoc-channel and has established transparency of transmission in the direction iom ? -2 to u-interface. the downstream device is requested to start the activation procedure and to establish a loopback #2. dc deactivation confirmation idle code on the iom ? -2-interface. dr deactivation request the u-transceiver has detected a deactivation request command from the lt-side for a complete deactivation or a s/t only deactivation. the downstream device is requested to start the deactivation procedure. ei1 error indication 1 the u-transceiver has entered a failure condition caused by loss of framing on the u-interface or expiry of timer t1. signals on u-interface the signals snx, tn and sp transmitted on the u-interface are defined in table 9 . table 9 u-interface signals signal synch. word (sw) superframe (isw) 2b + d m-bits tn 1) 3 3 3 3 sn0 no signal no signal no signal no signal sn1 present absent 1 1 sn2 present absent 1 1 sn3 present present 1 normal
pef 80912/80913 functional description data sheet 25 2001-03-29 note: 1) alternating 3 symbols at 10 khz. note: 2) a series of single pulses spaced at intervals of 1.5 ms; alternating +/-3. input signals of the state machine and related u-signals the table below summarizes the input signals that control the nt state machine and that are extracted from the u-interface signal sequences. sn3t present present normal normal test mode sp 2) test signal test signal test signal test signal lof loss of framing this condition is fulfilled if framing is lost for 573 ms. lsec loss of signal behind echo canceller internal signal which indicates that the echo canceller has converged lsu loss of signal on u-interface this signal indicates that a loss of signal level for a duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where the nt waits for a response (no signal level) from the lt- side. lsue loss of signal on u-interface - error condition after a loss of signal has been noticed, a 588 ms timer is started. when it has elapsed , the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the nt is not prepared to lose signal level i.e. the lt has stopped transmission because of loss of framing, an unsuccessful activation, or the transmission line is interrupted. fd frame detected sfd super frame detected table 9 u-interface signals (cont ? d) signal synch. word (sw) superframe (isw) 2b + d m-bits
pef 80912/80913 functional description data sheet 26 2001-03-29 signals on iom ? -2 the data (b+b+d) is set to all ? 1 ? s in all states besides the states listed in table 10 . : dependence of outputs outputs denoted with 1) in figure 10 : signal output on u k0 depends on the received eoc command and on the history of the state machine according to table 11 : bbd0 / bbd1 bbd0/1 detected these signals are set if either ? 1' (bbd1) or ? 0' (bbd0) were detected in 4 subsequent basic frames. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd0 corresponds to the received signal sl2 in case of a normal activation, bbd1 corresponds to the internally received signal sn3 in case of analog loop back. tl awake tone detected the u-transceiver is requested to start an activation procedure. table 10 states with operational data on iom ? -2 synchronized1 synchronized2 wait for act transparent error s/t pend. deac. s/t pend. deac. u analog loop back table 11 signal output on u k0 eoc command history of the state machine signal output on u k0 received ? lbbd ? no influence sn3t received no ? lbbd ? or ? rtn ? after an ? lbbd ? state ? transparent ? has not been reached previously during this activation procedure sn3 state ? transparent ? has been reached previously during this activation procedure sn3t
pef 80912/80913 functional description data sheet 27 2001-03-29 outputs denoted with 2) in figure 10 : c/i-code output depends on received eoc-command ? lbbd ? according to table 12 : outputs denoted with 3) in figure 10 : in states ? pend. deact. s/t ? and ? pend. deact. u ? the act-bit output depends on its value in the previous state. the value of the issued sai-bit depends on the received c/i-code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity of the downstream device. if state alerting is entered from state deactivated, then c/i-code ? pu ? is issued, else c/i-code ? dc ? is issued. 2.3.5.5 description of the nt-states the following states are used: alerting the wake-up signal tn is transmitted for a period of t11 either in response to a received wake-up signal tl or to start an activation procedure on the lt-side. alerting 1 ? alerting 1 ? state is entered when a wake-up tone was received in the ? receive reset ? state and the deactivation procedure on the nt-side was not yet finished. the transmission of wake-up tone tn is started. analog loop-back transparency is achieved in both directions of transmission. this state can be left by making use of any unconditional command. deactivated only in state deactivated the device may enter the power-down mode. table 12 c/i-code output eoc command synchroni zed 2 wait for act transparent error s/t received no ? lbbd ? or ? rtn ? after an ? lbbd ? ar ar ai ar received ? lbbd ? arl arl ail arl
pef 80912/80913 functional description data sheet 28 2001-03-29 ec training the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. ec-training 1 the ? ec-training 1 ? state is entered if transmission of signal sn1 has to be started and the deactivation procedure on the nt-side is not yet finished. ec-training al the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. eq-training the receiver waits for signal sl1 or sl2 to be able to update the agc, to recover the timing phase, to detect the synch-word (sw), and to update the eq-coefficients. error s/t the downstream device is in an error condition (ei1). the lt-side is informed by setting the act-bit to ? 0 ? (loss of transparency on the nt-side). iom ? -2-awaked the u-transceiver is deactivated, but may not enter the power-down mode. pending deactivation of s/t the u-transceiver has received the uoa-bit at zero after a complete activation of the s/ t-interface. the u-transceiver requests the downstream device to deactivate by issuing dr. pending deactivation of u-interface the u-transceiver waits for the receive signal level to be turned off (lsu) to start the deactivation procedure. pending receive reset the ? pending receive reset ? state is entered upon detection of loss of framing on the u-interface or expiry of timer t1. this failure condition is signalled to the lt-side by turning off the transmit level (sn0). the u-transceiver then waits for a response (no signal level lsu) from the lt-side.
pef 80912/80913 functional description data sheet 29 2001-03-29 pending timing in the nt-mode the pending timing state assures that the c/i-channel code dc is issued four times before entering the ? deactivated ? state. receive reset in state ? receive reset ? a reset of the uk0-receiver is performed, except in case that state ? receive reset ? was entered from state ? pend. deact. u ? . timer t7 assures that no activation procedure is started from the nt-side for a minimum period of time of t7. this gives the lt a chance to activate the nt. reset in state ? reset ? a software-reset is performed. synchronized 1 state ? synchronized 1 ? is the fully active state of the u-transceiver, while the downstream device is deactivated. synchronized 2 in this state the u-transceiver has received uoa = 1. this is a request to activate the downstream device. test the test signal ssp is issued as long as tm2-0 = ? 101 ? . for further details see table 9 . transparent this state is entered upon the detection of act = 1 received from the lt-side and corresponds to the fully active state. wait for act upon the receipt of ai, the nt waits for a response (act = 1) from the lt-side. wait for sf the signal sn2 is sent on the u-interface and the receiver waits for detection of the superframe. wait for sf al this state is entered in the case of an analog loop-back and allows the receiver to update the agc, to recover the timing phase, and to update the eq-coefficients.
pef 80912/80913 functional description data sheet 30 2001-03-29 2.3.6 metallic loop termination for north american applications a maintenance controller according to ansi t1.601 section 6.5 is implemented. the maintenance pulse stream from the u-interface metallic loop termination circuit (mlt) is fed to pin mti, usually via an optocoupler. it is digitally filtered for 20 ms and decoded independently on the polarity by the maintenance controller according to table 13 . therefore, the maintenance controller is capable of detecting the dc and ac signaling format. the q-smint ? o automatically sets the u- transceiver in the proper state and issues an interrupt. the state selected by the mlt is indicated via two bits. the q-smint ? o reacts on a valid pulse stream independently of the current u- transceiver state. this includes the power-down state. a test mode is valid for 75 seconds. if during the 75 seconds a valid pulse sequence is detected the 75 s timer starts again. after expiry of the 75 s timer the mlt maintenance controller goes back to normal operation. figure 11 shows examples for pulse streams with inverse polarity selecting quiet mode. table 13 ansi maintenance controller states number of counted pulses ansi maintenance controller state u-transceiver state machine <= 5 ignored no impact 6 quiet mode transition to state ? reset ? start timer 75s 7 ignored no impact 8 insertion loss measurement transition to state ? transparent ? start timer 75s 9 ignored no impact 10 normal operation transition to state ? reset ? >= 11 ignored no impact
pef 80912/80913 functional description data sheet 31 2001-03-29 figure 11 pulse streams selecting quiet mode mlt.vsd pin mti 1 1 5 4 3 26 500 ms 500 ms 0 pin mti 1 1 20 ms < t high < 500 ms 5 4 3 26 500 ms 500 ms 0 4ms pef 80912/80913 functional description data sheet 32 2001-03-29 2.4 s-transceiver the s-transceiver offers the nt state machine described in the user ? s manual v3.4 [10]. the s-transceiver basic configurations are performed via pin strapping. 2.4.1 line coding, frame structure line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. figure 12 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 12 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. 011 code violation
pef 80912/80913 functional description data sheet 33 2001-03-29 figure 13 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. 2.4.2 s/q channels, multiframing the s/q channels are not supported. ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multi-frame f a
pef 80912/80913 functional description data sheet 34 2001-03-29 2.4.3 data transfer between iom ? -2 and s 0 in the state g3 (activated) the b1, b2 and d bits are transferred transparently from the s/t to the iom ? -2 interface and vice versa. in all other states ? 1 ? s are transmitted to the iom ? -2 interface. 2.4.4 loopback 2 c/i commands arl and ail close the analog loop as close to the s-interface as possible. etsi refers to this loop under ? loopback 2 ? . etsi requires, that b1, b2 and d channels have the same propagation delay when being looped back. the d-channel echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). the loop is transparent. note: after c/i-code ail has been recognized by the s-transceiver, zeros are looped back in the b and d-channels (du) for four frames. 2.4.5 state machine the state diagram notation is given in figure 14 . the information contained in the state diagrams are: ? state name ? signal received from the line interface (info) ? signal transmitted to the line interface (info) ? c/i code received (commands) ? c/i code transmitted (indications) ? transition criteria the transition criteria are grouped into: ? c/i commands ? signals received from the line interface (infos) ? reset
pef 80912/80913 functional description data sheet 35 2001-03-29 figure 14 state diagram notation as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? ? stands for a logical and combination. and a ? + ? indicates a logical or combination. test signals 2 khz single pulses (tm1) one pulse with a width of one bit period per frame with alternating polarity. 96 khz continuous pulses (tm2) continuous pulses with a pulse width of one bit period. note: the test signals tm1 and tm2 can be generated via pins tm0-2 according to table 5 . reset states after an active signal on the reset pin rst the s-transceiver state machine is in the reset state. c/i codes in reset state in the reset state the c/i code 0000 (tim) is issued. this state is entered after a hardware reset (rst ). c/i codes in deactivated state if the s-transceiver is in state ? deactivated ? and receives i0 , the c/i code 0000 (tim) is issued until expiration of the 8 ms timer. otherwise, the c/i code 1111 (di) is issued. iom-2 interface c/i code macro_17.vsd state ind. cmd. i x i r s/t interface info in out unconditional transition
pef 80912/80913 functional description data sheet 36 2001-03-29 receive infos on s/t i0 info 0 detected i0 level detected (signal different to i0) i3 info 3 detected i3 any info other than info 3 transmit infos on s/t i0 info 0 i2 info 2 i4 info 4 it send single pulses (tm1). send continuous pulses (tm2).
pef 80912/80913 functional description data sheet 37 2001-03-29 2.4.5.1 state machine nt mode figure 15 state machine nt mode note: by setting the test mode pins tm0-2 to ?010? / ?011?: continuous pulses / single pulses, the s-transceiver starts sending the corresponding test signal, but no state transition is invoked. g2 pend. act ar ard i2 i3 reset tim res i0 * g1 i0 detected ar dc i0 * g2 lost framing s/t rsy aid ard i2 i3 g1 deactivated di tim dc i0 i0 statem_nt_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 i3*aid 2) rst ard 1) g2 wait for aid ai ard i2 i3 g3 lost framing u rsy rsy i2 * g3 activated ai aid i4 i3 ard 1) aid 2) i3*ard 1) i3*ard dr dr dr rsy rsy dr rsy ard 1) aid 2) 1) : ard = ar or arl 2) :aid=aiorail ard 1) i3*aid 2) (i0*8ms)
pef 80912/80913 functional description data sheet 38 2001-03-29 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom ? -2 interface. g1 i0 detected an info 0 is detected on the s/t-interface, translated to an ? activation request ? indication in the c/i channel. the s-transceiver is waiting for an ar command, which normally indicates that the transmission line upstream is synchronized. g2 pending activation as a result of the ard command, an info 2 is sent on the s/t-interface. info 3 is not yet received. in case of arl command, loop 2 is closed. g2 wait for aid info 3 was received, info 2 continues to be transmitted while the s-transceiver waits for a ? switch-through ? command aid from the device upstream. g3 activated info 4 is sent on the s/t-interface as a result of the ? switch through ? command aid: the b and d-channels are transparent. on the command ail, loop 2 is closed. g2 lost framing s/t this state is reached when the transceiver has lost synchronism in the state g3 activated. g3 lost framing u on receiving an rsy command which usually indicates that synchronization has been lost on the transmission line, the s-transceiver transmits info 2. g4 pending deactivation this state is triggered by a deactivation request dr, and is an unstable state. indication di (state ? g4 wait for dr ? ) is issued by the transceiver when: either info0 is received for a duration of 16 ms or an internal timer of 32 ms expires.
pef 80912/80913 functional description data sheet 39 2001-03-29 g4 wait for dr final state after a deactivation request. the s-transceiver remains in this state until dc is issued. unconditional states test mode tm1 send single pulses test mode tm2 send continuous pulses c/i commands command abbr. code remark deactivation request dr 0000 deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. activation indication ai 1100 activation indication. synchronous receiver, i.e. activation completed.
pef 80912/80913 functional description data sheet 40 2001-03-29 activation indication loop ail 1110 activation indication loop deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during deactivation procedure. receiver not synchronous rsy 0100 receiver is not synchronous. activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request. command abbr. code remark
pef 80912/80913 operational description data sheet 41 2001-03-29 3 operational description 3.1 layer 1 activation/deactivation 3.1.1 complete activation initiated by exchange figure 16 depicts the procedure if activation has been initiated by the exchange side (lt). figure 16 complete activation initiated by exchange iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc info 0 dc sl0 di info 0 di di itd10035.vsd sn0 sl0 pu arm sl2 (act = 0, dea = 1, uoa = 0) sn2 ar ar sn1 ar dc tn sn0 sl1 sn3 (act = 0, sai = 0) uai tl ar info 2 ai sl3t (act = 0, dea = 1, uoa = 1) sn3 (act = 1, sai = 1) info 3 ar sn3 (act = 0, sai = 1) sl3t (act = 0, dea = 1, uoa = 0) sn3t ai ai info 4 ai ar8/10 dc s 0 u k0 dfe-q sbcx-x or ipac-x q-sminto
pef 80912/80913 operational description data sheet 42 2001-03-29 3.1.2 complete activation initiated by te figure 17 depicts the procedure if activation has been initiated by the terminal side (te). figure 17 complete activation initiated by te iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc info 0 dc sl0 dc di info 0 di sn0 di tim pu ar8/10 info 1 tim pu ar ar info 2 rsy info 0 info 3 ar ai arm uai ai ai info 4 ai tn sn1 sn0 sl1 sl2 (act = 0, dea = 1, uoa = 0) sn2 sn3 (act = 0, sai = 1) sl3t (uoa = 1) sn3 (act = 1, sai = 1) sl3t (act = 1, dea = 1, uoa = 1) sn3t itd10041.vsd ar sbcx-x or ipac-x s 0 u k0 dfe-q 8ms dc q-sminto
pef 80912/80913 operational description data sheet 43 2001-03-29 3.1.3 complete deactivation figure 18 depicts the procedure if deactivation has been initiated. deactivation of layer 1 is always initiated by the exchange. figure 18 complete deactivation initiated by exchange iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 ai info 4 ai sl3t (act = 1, dea = 1, uoa = 1) ar ar info 3 ai ai tim itd10040.vsd dc sn3t(act=1,sai=1) dr deac sl3t (act = 0, dea = 0) sl0 40 ms sn0 3ms dr info 0 dc di dc di sbcx-x or ipac-x s 0 u k0 dfe-q info 0 di & dr rsy 1) c/i-codearmightbeissuedbeforec/i-codedcincaseof m4 validation algorithm crc&tll is selected dc 1) q-sminto
pef 80912/80913 operational description data sheet 44 2001-03-29 3.1.4 partial activation figure 19 depicts the procedure if partial activation has been initiated by the exchange. figure 19 partial activation iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc info 0 dc sl0 di info 0 di di itd10036.vsd sn0 tl pu arm sl2 (act = 0, dea = 1, uoa = 0) sn2 uar dc sn1 ar dc tn sn0 sl1 sn3 (act = 0, sai = 0) sl3t (act = 0, dea = 1, uoa = 0) uai (dc) sl0 sbcx-x or ipac-x dfe-q s 0 u k0 q-sminto
pef 80912/80913 operational description data sheet 45 2001-03-29 3.1.5 activation from exchange with u active figure 20 depicts the procedure if activation has been initiated by the exchange with u already being active. figure 20 activation from lt with u active iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc info 0 dc sl3t (act = 0, dea = 1, uoa = 0) dc/uar di info 0 di uai itd10037.vsd sn3 (act = 0, sai = 0) sl3t (act = 0, dea = 1, uoa = 1) ar info 2 ai ar uai ai info 3 sn3 (act = 1, sai = 1) sl3t (act = 1, dea = 1, uoa = 1) ai info 4 ai sn3t ar ar sn3 (act = 0, sai = 1) ar ar8/10 u k0 s 0 dfe-q sbcx-x or ipac-x q-sminto
pef 80912/80913 operational description data sheet 46 2001-03-29 3.1.6 activation from te with u active figure 21 depicts the procedure if activation has been initiated by the te with u already being active. figure 21 activation from te with u active iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc info 0 dc sl3t (act = 0, dea = 1, uoa = 0) uar di info 0 di uai sn3 (act = 0, sai = 0) tim ar8/10 info 1 tim pu s 0 u k0 ar 8ms itd10038.vsd sn3 (act = 0, sai = 1) sl3t (act = 0, dea = 1, uoa = 1) info 2 info 0 ai rsy ar uai ai info 3 sn3 (act = 1, sai = 1) sl3t (act = 1, dea = 1, uoa = 1) ai info 4 ai sn3t ar ar sbcx-x or ipac-x dfe-q q-sminto
pef 80912/80913 operational description data sheet 47 2001-03-29 3.1.7 partial deactivation with u active figure 22 depicts the procedure if partial deactivation has been initiated by the exchange; i.e. u remains active. figure 22 partial deactivation with u active iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 ai info 4 ai sl3t (act = 1, dea = 1, uoa = 1) ar ar info 3 ai ai tim itd10039.vsd sn3t(act=1,sai=1) uar sl3t (act = 1, dea = 1, uoa = 0) dr info 0 info 0 di dc dr di dc uai sn3t(act=0,sai=0) sl3t (act = 0, dea = 1, uoa = 0) dfe-q u k0 s 0 sbcx-x or ipac-x sn3t(act=1,sai=0) q-sminto
pef 80912/80913 operational description data sheet 48 2001-03-29 3.1.8 loop 2 figure 23 depicts the procedure if loop 2 is closed and opened. figure 23 loop 2 note: closing / resolving loop 2 may provoke the s-transceiver to resynchronize. in this case, the following c/i-codes are exchanged immediately upon receipt of ail / ai, respectively: du: ?rsy?, dd: ?arl?, du: ?ai?, dd: ?ail? / ?ai?. iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 ai info 4 sl3t (act = 1, dea = 1, uoa = 1) ar8/10 info 3 ai itd10042.vsd sn3t (act = 1, sai = 1) ar ai ai 2b+d 2b+d 2b+d ail lp2i = 0 eoc: lbbd; act = 1 mon0: lbbd ai eoc: rtn; act = 1 mon0: rtn lp2i = 1 sbcx-x or ipac-x s 0 u k0 dfe-q q-sminto
pef 80912/80913 operational description data sheet 49 2001-03-29 3.2 layer 1 loopbacks test loopbacks are specified by the national ptts in order to facilitate the location of defect systems. four different loopbacks are defined. the position of each loopback is illustrated in figure 24 . figure 24 test loopbacks loopbacks #1, #1a and #2 are controlled by the exchange. loopback #3 is controlled locally on the remote side. all four loopback types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. only the data looped back internally is processed; signals on the receive pins are ignored. the propagation delay of actually looped b and d channels data must be identical in all loopbacks. iom ? -2 pbx or te u-transceiver iom ? -2 iom ? -2 iom ? -2 u-transceiver u-transceiver u-transceiver u-transceiver u-transceiver loop 2 loop 3 loop 2 loop 1 a loop 2 loop 1 s-bus nt u u loop 2 repeater (optional) s-transceiver layer-1 controller layer-1 controller iom-2 exchange loop_2b1q.emf
pef 80912/80913 operational description data sheet 50 2001-03-29 3.2.1 loopback no.2 for loopback #2 several alternatives exist. both the type of loopback and the location may vary. the following loopback types belong to the loopback-#2 category: complete loopback (b1,b2,d), in a downstream device b1-channel loopback, always performed in the u-transceiver b2-channel loopback, always performed in the u-transceiver all loop variations performed by the u-transceiver are closed as near to the internal iom ? -2 interface as possible. normally loopback #2 is controlled by the exchange. the maintenance channel is used for this purpose. all loopback functions are latched. this allows channel b1 and channel b2 to be looped back simultaneously. 3.2.1.1 complete loopback when receiving the request for a complete loopback, the u transceiver passes it on to the downstream device, e.g. the s-bus transceiver. this is achieved by issuing the c/i- code ail in the ? transparent ? state or c/i = arl in states different than ? transparent ? 3.2.1.2 loopback no.2 - single channel loopbacks single channel loopbacks are always performed directly in the u-transceiver. no difference between the b1-channel and the b2-channel loopback control procedure exists.
pef 80912/80913 operational description data sheet 51 2001-03-29 3.3 external circuitry 3.3.1 power supply blocking recommendation the following blocking circuitry is suggested. figure 25 power supply blocking 3.3.2 u-transceiver the q-smint ? o is connected to the twisted pair via a transformer. figure 26 shows the recommended external circuitry. the recommended protection circuitry is not displayed. note: the integrated hybrid as specified for version 1.1 is no more available in version 1.3 and an external hybrid is required. vddd vddd vssd vssd vdda_sr vdda_ur vdda_ux vdda_sx vssa_ur vssa_ux vssa_sr vssa_sx 100nf 100nf 100nf 100nf 100nf 100nf gnd 3.3v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) blocking_caps_smint.vsd
pef 80912/80913 operational description data sheet 52 2001-03-29 . figure 26 external circuitry u-transceiver u-transformer parameters the following table 14 lists parameters of typical u-transformers: table 14 u-transformer parameters u-transformer parameters symbol value unit u-transformer ratio; device side : line side n1 : 2 main inductance of windings on the line side l h 14.5 mh leakage inductance of windings on the line side l s <75 h coupling capacitance between the windings on the device side and the windings on the line side c k 100 pf dc resistance of the windings on device side r b 2.5 1) ? dc resistance of the windings on line side r l 5 1) 1) r b / r l according to equation[2] ? loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf
pef 80912/80913 operational description data sheet 53 2001-03-29 resistors of the external hybrid r3, r4 and r t r3 = 1.3 k ? r4 = 1.0 k ? r t = 9.5 ? resistors on the line side r ptc / chip side r t optional use of up to 2x20 ? resistors (2xr ptc ) on the line side of the transformer requires compensation resistors r comp depending on r ptc : 2r ptc + 8r comp = 40 ? (1) 2r ptc + 4(2r comp + 2r t + r out + r b ) + r l = 135 ? (2) r b , r l : see table 14 r out : see table 19 27 nf capacitor c to achieve optimum performance the 27 nf capacitor should be mkt. a ceramic capacitor is not recommended. tolerances rs: 1% c=27 nf: 10-20% l=14.5 mh: 10% 3.3.3 s-transceiver in order to comply to the physical requirements of itu recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the s-transceiver needs some additional circuitry. s-transformer parameters the following table 15 lists parameters of a typical s-transformer:
pef 80912/80913 operational description data sheet 54 2001-03-29 table 15 s-transformer parameters transmitter the transmitter requires external resistors r stx = 47 ? in order to adjust the output voltage to the pulse mask (nominal 750 mv according to itu i.430, to be tested with the test mode ? tm1 ? ) on the one hand and in order to meet the output impedance of minimum 20 ? on the other hand (to be tested with the testmode ? continuous pulses ? ) on the other hand. note: the resistance of the s-transformer must be taken into account when dimensioning the external resistors r stx . if the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. figure 27 external circuitry s-interface transmitter transformer parameters symbol value unit transformer ratio; device side : line side n2 : 1 main inductance of windings on the line side l h typ. 30 mh leakage inductance of windings on the line side l s typ. <3 h coupling capacitance between the windings on the device side and the windings on the line side c k typ. <100 pf dc resistance of the windings on device side r b typ. 2.4 ? dc resistance of the windings on line side r l typ. 1.4 ? 20...40 47 sx1 sx2 2:1 gnd v dd 47 dc point extcirc_s.vsd
pef 80912/80913 operational description data sheet 55 2001-03-29 receiver the receiver of the s-transceiver is symmetrical. 10 k ? overall resistance are recommended in each receive path. it is preferable to split the resistance into two resistors for each line. this allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 khz input impedance test of itu i.430 [8] and ets 300012-1). the remaining resistance (1.8 k ? ) protects the s- transceiver itself from input current peaks. figure 28 external circuitry s-interface receiver 3.3.4 oscillator circuitry figure 29 illustrates the recommended oscillator circuit. figure 29 crystal oscillator 1k8 1k8 sr1 sr2 2:1 gnd v dd 8k2 8k2 dc point extcirc_s.vsd 15.36 mhz xout xin c ld c ld
pef 80912/80913 operational description data sheet 56 2001-03-29 table 16 crystal parameters external components and parasitics the load capacitance c l is computed from the external capacitances c ld , the parasitic capacitances c par (pin and pcb capacitances to ground and v dd ) and the stray capacitance c io between xin and xout: for a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances c ld , which is usually the only variable to be determined by the circuit designer. typical values for the capacitances c ld connected to the crystal are 22 - 33 pf. 3.3.5 general low power leds mlt input supports ? apc13112 ? at&t lh1465ab ? discrete as proposed by infineon parameter symbol limit values unit frequency f 15.36 mhz frequency calibration tolerance +/-60 ppm load capacitance c l 20 pf max. resonance resistance r1 20 ? max. shunt capacitance c 0 7pf oscillator mode fundamental c l c ld c par + () c ld c par + () c ld c par + () c ld c par + () + ------------------------------------------------------------------------ c io + =
pef 80912/80913 electrical characteristics data sheet 57 2001-03-29 4 electrical characteristics 4.1 absolute maximum ratings esd integrity (according eia/jesd22-a114b (hbm)): 2 kv note: stress above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. line overload protection the q-smint ? o is compliant to esd tests according to ansi / eos / esd-s 5.1-1993 (cdm), eia/jesd22-a114b (hbm) and to latch-up tests according to jedec eia / jesd78. from these tests the following max. input currents are derived ( table 17 ): parameter symbol limit values unit ambient temperature under bias t a -40 to 85 c storage temperature t stg ? 65 to 150 c maximum voltage on v dd v dd 4.2 v maximum voltage on any pin with respect to ground v s -0.3 to v dd + 3.3 (max. < 5.5) v table 17 maximum input currents test pulse width current remarks esd 100 ns 1.3 a 3 repetitions latch-up 5 ms +/-200 ma 2 repetitions, respectively dc -- 10 ma
pef 80912/80913 electrical characteristics data sheet 58 2001-03-29 4.2 dc characteristics table 18 s-transceiver characteristics v dd / v dda = 3.3 v +/- 5% ; v ss / v ssa = 0 v; t a = -40 to 85 c digital pins parameter symbol limit values unit test condition min. max. all input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 5.25 v all except dd/du act ,lp2i mclk output low voltage v ol1 0.45 v i ol1 = 3.0 ma output high voltage v oh1 2.4 v i oh1 = 3.0 ma dd/du act ,lp2i mclk output low voltage v ol2 0.45 v i ol2 = 4.0 ma output high voltage (dd/du push-pull) v oh2 2.4 v i oh2 = 4.0 ma all input leakage current i li 10 a 0 v v in v dd output leakage current i lo 10 a 0 v v in v dd input leakage current (internal pull-up) i lipu 50 200 a 0 v v in v dd analog pins ain, bin input leakage current i li 70 a 0 v v in v d d pin parameter symbol limit values unit test condition min. typ. max. sx1,2 absolute value of output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.2 2.31 v r l = 50 ? sx1,2 s-transmitter output impedance z x 10 34 k ? see 1) 0 see 2)3) sr1,2 s-receiver input impedance z r 10 100 k ? ? v dd = 3.3 v v dd = 0 v
pef 80912/80913 electrical characteristics data sheet 59 2001-03-29 table 19 u-transceiver characteristics 1) requirement itu-t i.430, chapter 8.5.1.1a): ? at all times except when transmitting a binary zero, the output impedance , in the frequency range of 2khz to 1 mhz, shall exceed the impedance indicated by the template in figure 11. the requirement is applicable with an applied sinusoidal voltage of 100 mv (r.m.s value) ? 2) requirement itu-t i.430, chapter 8.5.1.1b): ? when transmitting a binary zero, the output impedance shall be > 20 ? . ? : must be met by external circuitry. 3) requirement itu-t i.430, chapter 8.5.1.1b), note: ? the output impedance limit shall apply for a nominal load impedance (resistive) of 50 ? . the output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. the peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. the limitation applies for pulses of both polarities. ? limit values unit min. typ. max. receive path signal / (noise + total harmonic distortion) 1) 1) test conditions: 1.4 vpp differential sine wave as input on ain/bin with long range (low, critical range). 65 2) 2) versions pef 8x913 with enhanced performance of the u-interface are tested with tightened limit values db dc-level at ad-output 45 50 55 % 3) 3) the percentage of the "1 "-values in the pdm-signal. threshold of level detect (measured between ain and bin with respect to zero signal) 4 5 16 (pef 80912) mv peak 9 (pef 80913) input impedance ain/bin 80 k ? transmit path signal / (noise + total harmonic distortion) 4) 4) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 70 db below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. 70 db common mode dc-level 1.61 1.65 1.69 v offset between aout and bout 35 mv absolute peak voltage for a single +3 or -3 pulse measured between aout and bout 5) 2.42 2.5 2.58 v output impedance aout/bout: power-up power-down 0.8 3 1.5 6 ? ?
pef 80912/80913 electrical characteristics data sheet 60 2001-03-29 4.3 capacitances t a = 25 c, 3.3 v 5 % v ssa = 0 v, v ssd = 0 v, f c = 1 mhz, unmeasured pins grounded. 4.4 power consumption 5) the signal amplitude measured over a period of 1 min. varies less than 1%. table 20 pin capacitances parameter symbol limit values unit remarks min. max. digital pads: input capacitance i/o capacitance c in c i/o 7 7 pf pf analog pads: load capacitance c l 3 pf pin ain, bin power consumption vdd=3.3 v, vss=0 v, inputs at vss/vdd, no led connected, 50% bin. zeros, no output loads except sx1,2 (50 ? 1) ) 1) 50 ? (2 x tr) on the s-bus. parameter limit values unit test condition min. typ. max. operational u and s enabled, iom ? -2 off 235 200 mw mw u: etsi loop 1 (0 m) u: etsi loop 2.(typical line) power down 15 mw
pef 80912/80913 electrical characteristics data sheet 61 2001-03-29 4.5 supply voltages vdd d = + vdd 5% vdd a = + vdd 5% the maximum sinusoidal ripple on vdd is specified in the following figure: figure 30 maximum sinusoidal ripple on supply voltage 80 100 frequency / khz 10 100 mv (peak) 200 supply voltage ripple frequency ripple itd04269.vsd 60
pef 80912/80913 electrical characteristics data sheet 62 2001-03-29 4.6 ac characteristics t a = -40 to 85 c, v dd = 3.3 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 31 . figure 31 input/output waveform for ac tests parameter all output pins symbol limit values unit min max fall time 30 ns rise time 30 ns device under test c load =50 pf 2.4 0.45 2.0 0.8 0.8 2.0 test points its00621.vsd
pef 80912/80913 electrical characteristics data sheet 63 2001-03-29 4.6.1 iom-2 interface figure 32 iom ? -2 interface - bit synchronization timing figure 33 iom-2 interface - frame synchronization timing note: at the start and end of a reset period, a frame jump may occur. this results in a dcl and fsc high time of min. 130 ns after this specific event. t 7 dcl last bit first bit du/dd (output) t 6 t 8 bit n bit n+1 du/dd (output) fsc dcl t 9 t 10 t 2 t 3 t 1
pef 80912/80913 electrical characteristics data sheet 64 2001-03-29 parameter iom ? -2 interface symbol limit values unit min typ max dcl period t 1 1875 1953 2035 ns dcl high t 2 850 960 1105 ns dcl low t 3 850 960 1105 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 100 ns output data from active to high impedance t 7 100 ns output data delay from clock t 8 80 ns fsc high t 9 50% of fsc cycle time ns fsc advance to dcl t 10 65 130 195 ns dcl, fsc rise/fall t 15 30 ns data out rise/fall (c l = 50 pf, tristate) t 17 150 ns
pef 80912/80913 electrical characteristics data sheet 65 2001-03-29 4.6.2 reset table 21 reset input signal characteristics figure 34 reset input signal parameter symbol limit values unit test conditions min. typ. max. length of active low state t rst 4 ms power on the 4 ms are assumed to be long enough for the oscillator to run correctly 2 x dcl clock cycles + 400 ns after power on t rst rst itd09823.vsd
pef 80912/80913 electrical characteristics data sheet 66 2001-03-29 4.6.3 undervoltage detection characteristics figure 35 undervoltage control timing v dd v ddmin v det t t rsto t act t act t deact t deact v hys vdddet.vsd
pef 80912/80913 electrical characteristics data sheet 67 2001-03-29 table 22 parameters of the uvd/por circuit v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. detection threshold 1) 1) the detection threshold v det is far below the specified supply voltage range of analog and digital parts of the q-smint ? o. therefore, the board designer must take into account that a range of voltages is existing, where neither performance and functionality of the q-smint ? o are guaranteed, nor a reset is generated. v det 2.7 2.8 2.92 v v dd = 3.3 v 5 % hysteresis v hys 30 90 mv max. rising/falling v dd edge for activation/ deactivation of uvd dv dd /dt 0.1 v/s max. rising v dd for power-on 2) 2) if the integrated power-on reset of the q-sminto is selected (vdddet = ? 0 ? ) and the supply voltage v dd is ramped up from 0v to 3.3v +/- 5%, then the q-sminto is kept in reset during v ddmin < v dd < v det + v hys . v dd must be ramped up so slowly that the q-sminto leaves the reset state after the oscillator circuit has already finished start-up. the start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. 0.1 v/ ms min. operating voltage v ddmin 1.5 v delay for activation of rsto t act 10 s delay for deactivation of rsto t deact 64 ms
pef 80912/80913 package outlines data sheet 68 2001-03-29 5 package outlines plastic package, p-mqft-44 (metric quad flat package)
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 69 2001-03-29 6 appendix: differences between q- and t-smint ? o the q- and t-smint ? o have been designed to be as compatible as possible. however, some differences between them are unavoidable due to the different line codes 2b1q and 4b3t used for data transmission on the u k0 line. especially the pin compatibility between q- and t-smint ? o allows for one single pcb design for both series with only some mounting differences. the following chapter summarizes the main differences between the q- and t- smint ? o. 6.1 pinning table 23 pin definitions and functions pin mqft-44 q-smint ? o: 2b1q t-smint ? o: 4b3t 10 triple-last-look (tll )tie to ? 1 ? 11 metallic termination input (mti) tie to ? 1 ? 16 auto u activation (aua) tie to ? 1 ? 17 cold start only (cso) tie to ? 1 ? 38 power status (primary) (ps1) tie to ? 1 ? 26 power status (secondary) (ps2) tie to ? 1 ?
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 70 2001-03-29 6.2 u-transceiver 6.2.1 u-interface conformity table 24 related documents to the u-interface document q-smint ? o: 2b1q t-smint ? o: 4b3t etsi: ts 102 080 conform to annex a compliant to 10 ms interruptions conform to annex b ansi: t1.601-1998 (revision of ansi t1.601- 1992) conform mlt input and decode logic not required cnet: st/laa/elr/dnp/ 822 conform not required rc7355e conform not required ftz-richtlinie 1 tr 220 not required conform
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 71 2001-03-29 6.2.2 u-transceiver state machines figure 36 ntc-q compatible state machine q-smint ? o: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e&di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 72 2001-03-29 figure 37 iec-t/ntc-t compatible state machine t-smint ? o: 4b3t awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 synchronizing rsy (u0 & t12e) u2 t12s t13e u1a ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai/ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 73 2001-03-29 6.2.3 command/indication codes table 25 c/i codes code q-smint ? o: 2b1q t-smint ? o: 4b3t in out in out 0000 tim dr tim dr 0001 res ??? 0010 ???? 0011 ???? 0100 ei1 ei1 ? rsy 0101 ssp ? ssp ? 0110 dt ? dt ? 0111 ? pu ?? 1000 ar ar ar ar 1001 ???? 1010 arl arl ? arl 1011 ???? 1100 ai ai ai ai 1101 ?? res ? 1110 ? ail ? ail 1111 di dc di dc
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 74 2001-03-29 6.3 external circuitry the external circuitry of the q- and t-smint ? o is equivalent; however, some external components of the u-transceiver hybrid must be dimensioned different for 2b1q and 4b3t. all information on the external circuitry is preliminary and may be changed in future documents. figure 38 external circuitry q- and t-smint ? o the necessary protection circuitry is not displayed in figure 38 loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf
pef 80912/80913 appendix: differences between q- and t-smint ? o data sheet 75 2001-03-29 table 26 dimensions of external components. component q-smint ? o: 2b1q t-smint ? o: 4b3t transformer: ratio main inductivity 1:2 14.5 mh 1:1.6 7.5 mh resistance r3 1.3 k ? 1.75 k ? resistance r4 1.0 k ? 1.0 k ? resistance r t 9.5 ? 25 ? capacitor c 27 nf 15 nf r ptc and r comp 2r ptc + 8r comp = 40 ? n 2 (2r comp + r b ) + r l = 20 ?
pef 80912/80913 index data sheet 76 2001-03-29 7index a absolute maximum ratings 57 b block diagram 6 c c/i codes u-transceiver 19 cyclic redundancy check 18 d dc characteristics 58 differences between q- and t-smint 69 e external circuitry s-transceiver 53 u-transceiver 51 f features 3 i iom ? -2 interface ac characteristics 63 frame structure 14 functional description 14 l layer 1 loopbacks 49 led pins 10 line overload protection 57 m metallic loop termination 30 o oscillator circuitry 55 p package outlines 68 pin configuration 5 pin definitions and functions 7 power consumption 60 power supply blocking 51 power-on reset 13, 66 r reset generation 13 input signal characteristics 65 power-on reset 13, 66 under voltage detection 13, 66 s s/q channels 33 scrambling/ descrambling 18 s-transceiver functional description 32 state machine, nt 37 supply voltages 61 system integration 12 t test modes 11 u u-interface hybrid 51 under voltage detection 13, 66 u-transceiver functional description 15 state machine, standard nt 21
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